Micron’s technology roadmap: Staying with 6F², betting on hybrid bonding and AI memory expansion

Why is Micron sticking with 6F² instead of moving to 4F²?

At its technology symposium, Micron emphasized that its leadership now spans four consecutive generations of DRAM nodes, the performance and power consumption of three generations of HBM, and three generations of NAND since 2019. Deutsche Bank’s review focused on the path along which these advantages will continue to expand; its report rates Micron a “Buy” with a price target of 1,550 dollars.
As some competing roadmaps increasingly emphasize 4F², Micron has made clear that it has no plans to switch. The company believes capacitor pitch is the key determinant of DRAM density scaling, and that the benefits of changing the cell architecture alone can easily be overstated; the additional complexity and cost of 4F² are unlikely to deliver sufficient long-term density advantages.
This choice is based on years of evaluation and internal prototype development. Micron believes 6F² is more attractive until the industry eventually moves to 3D DRAM; Deutsche Bank interprets this as a clear rebuttal of competitors’ technology roadmaps.

Micron hopes to be among the first to adopt hybrid bonding, for reasons that extend beyond heat dissipation: as future HBM continues to increase bandwidth, energy efficiency and interconnect density, the technology is an important element supporting the scaling of system performance.
But a 16-layer stack does not correspond directly to a single process. Micron said future 16-layer HBM could use either microbumps or hybrid bonding, depending on customer and product requirements. Amid industry discussions about reduced memory specifications and potentially lower future HBM capacity, the company continues to stand by the long-term value of hybrid bonding.
Competition is also extending into logic integration. The company said its collaboration with foundry partners on next-generation HBM is progressing well, while it is investing in its own CMOS and logic capabilities; vHBM, which stacks memory directly on a processor or XPU, is a potential opportunity it sees. Deutsche Bank therefore emphasizes that differentiation is moving beyond the memory cell itself.

Management believes AI is expanding from the first round of training and early inference to next-generation inference, agents, robotics and edge applications. Capacity and bandwidth requirements are consequently spreading across more products, with opportunities including LPDDR, SOCAMM, SSDs and DIMMs; the company also plans to introduce a 1 TB RDIMM.
Product requirements differ across these use cases. Data centers focus on HBM bandwidth and performance, while physical AI and edge applications place greater emphasis on energy efficiency, latency, size and cost. Micron therefore needs a more diversified product roadmap rather than directly replicating hyperscale data center solutions across all endpoints.

Micron’s Gen11 NAND roadmap targets more than 400 layers, roughly twice the bit density and approximately 1.5 times the I/O speed of Gen9, and uses wafer-to-wafer bonding. Management sees it as a more significant architectural shift than in previous generations and plans to begin ramping it in the second half of 2027.
The business rationale is that the value of AI storage increasingly depends on its contribution to system performance, rather than solely on cost per bit. Micron noted that AI-oriented NAND products are being divided by application into high-IOPS and high-bandwidth categories to meet different data-access requirements.